English
Jordi Blasco organizes the workshop “Introduction to Intel Phi”. SIE support him allows to remote use the SIE Ladón 32C based on Intel 4600 Platform and Intel Phi 5110p board.
Jordi Blasco is HPC administrator in New Zealand eScience Infrastructure.
The Intel Xeon Phi coprocessor is suited for massive parallel applications that feature a high ratio of computation to data access. It is composed of up to 61 CPU cores and each core is capable of switching between up to 4 hardware threads on round-robin scheduling, resulting in a total of up to 244 hardware threads available. Each core consists of an slow processor with few extension capabilities (like pentium 4), dual-issue x86 pipeline, a local L1 and L2 cache, and a separate vector processing unit (VPU).
More information:
http://www.eresearch.org.nz/event/eresearch-nz-2013/introduction-to-intel-phi-workshop